Network operators are rethinking how they deploy 6G functions, shifting from specialized hardware to general-purpose silicon that can handle control plane tasks alongside real-time inference. Intel’s latest Xeon 6+ processor, codenamed Clearwater Forest, is designed for that shift—packing 288 efficiency cores into a single socket while supporting DDR5-8000 memory and PCIe 5.0 I/O.
The chip is built on a 12-chiplet architecture: ten compute tiles on Intel’s 18A process node, one base tile on Intel 3, and two I/O tiles on Intel 7. Each compute tile holds six modules of four Darkmont efficiency cores, delivering 24 E-cores per tile. The design relies on Foveros Direct 3D stacking for vertical connectivity and EMIB links for horizontal communication between tiles.
- Core architecture: 288 Darkmont E-cores (64 KB instruction cache each, wider front end, larger out-of-order window)
- Cache hierarchy: ~4 MB L2 per four-core group; total last-level cache can exceed 1 GB (~1,152 MB)
- I/O and memory: 96 PCIe 5.0 lanes, 64 CXL 2.0 lanes, 12 memory channels (DDR5-8000 target)
- Packaging: Foveros Direct 3D stacking, EMIB links for multi-tile communication
The combination of high core counts and large caches is aimed at sustaining many small, real-time inference tasks—critical for distributed cell processing in 6G networks. Intel claims this reduces the need for separate accelerators while keeping latency and power consumption within normal ranges.
For cloud providers, a dual-socket system can provision hundreds of VMs from a single package, increasing density without sacrificing performance. However, the lack of confirmed price points or availability dates leaves buyers in a cautious hold pattern—this is a technical showcase rather than an immediate purchase decision.
