Monday, May 25th 2026 AMD "Zen 7" IP to Use TSMC A14 Node and More Advanced Packaging by AleksandarK Today, 10:01 Discuss (2 ) AMD is gradually preparing to launch its next-generation "Zen 6" series of processors under the new EPYC "Venice" server CPU family. Meanwhile, development of the "Zen 7" architecture has been ongoing for quite some time, and it seems we are finally learning which manufacturing node AMD will use for this CPU generation. According to Taiwanese media outlet Commercial Times, AMD is reportedly considering TSMC's A14 node, officially utilizing the first angstrom-era node for its products. As readers may recall, AMD recently began high-volume production of its EPYC "Venice" on the 2 nm node, but with the upcoming "Zen 6" architecture. We have covered the advancements that "Zen 6" brings over the current "Zen 5," but the next-generation "Zen 7" is expected to elevate performance to a whole new level, especially with the power and performance enhancements of the new TSMC A14 node. For "Zen 7" CCD IP codenamed "Grimlock," AMD plans to make its CPU architecture more AI-relevant, allowing future processing workloads to better leverage the processing power of 16 CPU cores per CCD. Among the key features are AVX10 and ACE. AVX10 unifies AVX-512 and AVX2 features to improve performance and compatibility across vector math-heavy workloads. ACE, or Advanced Matrix Extensions for Matrix Manipulation, is an industry-standard matrix math instruction set that could be relevant to a wide range of devices, from smartphones to servers. Other ISA additions with Zen 7 include FRED (Flexible Return and Event Delivery), which replaces the current device interrupt model to reduce system-level latency. Zen 7 also implements ChkTag x86 Memory Tagging to counteract various memory-level data vulnerabilities caused by buffer overflows and use-after-free errors. FRED, in particular, was a noteworthy feature that Intel was working on for its x86S lightweight ISA standard. Finally, AMD is reportedly exploring various packaging technologies, including next-generation 3D V-Cache technology. The company is said to be evaluating Powertech's FOPLP (Fan-Out Panel-Level Packaging) solution. Powertech, a silicon packaging vendor based in Taiwan, is recognized as one of the leading OSAT companies. As AMD explores different supply chain providers, Powertech has reportedly emerged as a potential option. The company currently offers various FOPLP technologies, so we are eager to see what AMD might choose for its "Zen 7" designs as it seeks to shift away from TSMC's dominance in silicon packaging. Source: Commercial Times Taiwan Related News Tags: 2 nm A14 AMD AVX-512 AVX10 CPU EPYC IP Taiwan TSMC V-Cache Venice x86 Zen 6 Zen 7 Aug 4th 2025 AMD Readies 16-Core Ryzen 9000X3D CPU with 192 MB L3 Cache and 200 W TDP (355) Sep 3rd 2025 AMD "Zen 6" Processors to Use TSMC 2 nm Node for CCDs, 3 nm for IOD (66) Aug 22nd 2025 Melting 12VHPWR Connector Claims its First AMD RX 9070 XT Victim (109) Sep 18th 2025 NVIDIA Buys $5B Worth of Intel, RTX iGPUs Coming to x86, Shares up 25% (256) Sep 8th 2025 AMD Claims Arm ISA Doesn't Offer Efficiency Advantage Over x86 (97) Feb 19th 2026 AMD Ryzen 10000 "Olympic Ridge" to Debut with 6/8/10/12/16/20/24-Core "Zen 6" SKUs (126) Apr 16th 2026 AMD to Re-launch Ryzen 7 5800X3D as "AM4 10th Anniversary Edition" (156) Apr 21st 2026 No Ryzen 9950X3D2 for , Gamers Nexus, or ComputerBase (211) Nov 30th 2025 AMD Lists Ryzen 7 9850X3D CPU with 5.6 GHz Boost Frequency (148) Nov 11th 2025 AMD Confirms Zen 6 (2 nm) and Zen 7 with Efficiency Upgrades and New AI Features (83) Add your own 2 on AMD "Zen 7" IP to Use TSMC A14 Node and More Advanced Packaging #1 Chaitanya Given Zen6 is yet to launch, expecting Zen 7 to be atleast 2.5 years out in future. #2 ncrs FRED, in particular, was a noteworthy feature that Intel was working on for its x86S lightweight ISA standard.It was not exclusive to x86S and is available in Panther Lake, usable at least under Linux and was benchmarked by Phoronix.
